In communication systems an oscillator subsystem is used as a fundamental building block. Oscillators are commonly used for up or down frequency conversion. They are also essential subsystems for direct frequency modulators and many other systems. The quality of a fixed frequency oscillator is most often measured by the frequency accuracy and the phase noise performance. In communication systems the basic RF oscillator is used in conjunction with additional circuitry used to control the frequency of the oscillator. Free running RF oscillators do not have adequate frequency accuracy for most communication system requirements. It is well understood that crystal oscillators provide a high degree of frequency accuracy and phase noise performance. Therefore, it is common in prior art to lock the RF oscillator frequency to a lower frequency crystal oscillator and achieve the desired frequency stability. Some of the other highly sought after qualities include the ability to tune a single oscillator over a wide frequency range with a very fine frequency resolution control, and the ability to change the frequency very rapidly. Further, it is common to add phase modulation to an oscillator by changing the phase of the oscillator versus time. Numerous prior art methods exist for implementing oscillators with varying compromises and limitations. Some of those methods are described below.
The first common method is frequency multiplication wherein lower frequency crystal oscillator signals are converted to higher frequency signals using frequency multiplication. One example of this arrangement is described in detail hereinafter.
The second method uses a phase locked loop (PLL). PLLs are available in a variety of forms such as fixed modulus, dual modulus, and fractional N. Many integrated circuit implementations are available. One example of this arrangement is described in detail hereinafter. So the design objective is to set the loop bandwidth as wide as possible to track out as much close in phase noise as possible. Further out phase noise, outside the loop bandwidth, is limited by the oscillator phase noise characteristic. However, there is a compromise well understood by people skilled in the art. This compromise results from the fact that smaller frequency step size (higher resolution) requires division to a lower common phase detector frequency. A PLL with lower loop bandwidth thus has to be used which consequently degrades the phase noise. Phase modulation is achieved by adding a second control of the VCO frequency. This control will only work if the loop bandwidth is narrow enough to not track out the phase modulation that is added.
The third method is a digital delay lock loop (DLL). This has the advantage that the oscillator is suitable for implementation in an ASIC. A variable delay control is used in conjunction with the phase detector to lock the oscillator frequency to a multiple of the input reference frequency. One example of this arrangement is described in detail hereinafter this method suffers from limitations to the PLL implementation. It also faces additional problems with frequency agility as well as the jitter introduced by the delay lock loop because of mismatched delays. Phase modulation is generally not added to DLLs, but could be added to the reference input or after the loop filter similar to the PLL method.
The fourth method is known as direct digital synthesis (DDS). One example of this arrangement is described in detail hereinafter. This method results in very fine frequency resolution, but produces undesired spurious signals and the output signal frequency is limited by the speed of the DAC. The signal frequency for the DDS is limited to Nyquist frequency which is half of the clock frequency to the DAC. Output signal level drops as the Nyquist frequency is approached. Phase modulation bits are commonly available in DDSs.
A fifth method is through phase interpolation as described in U.S. Pat. No. 6,114,914. This method is limited in its factional capability and still uses a VCO, phase detector, and loop filter. Normal conflict between better phase noise and higher frequency resolution still exists for this method. The addition of phase modulation would have similar limitations to the PLL method.
In phase modulation systems it is understood in the art that it is desirable to control the shape of the phase change. Sudden phase changes result in splatter of energy outside the bandwidth allocated to the signal, and degrades other channels. It is common to digitally generate the phase modulation and shape it using digital filtering such as sin x/x. The resulting digital signal is processed through a Digital to Analog converter (DAC) using a conversion clock that is at least twice the rate of the phase change information. Using a low pass filter commonly referred to as a reconstruction filter, the conversion clock frequency and the aliasing components resulting from the DAC are filtered off to reconstruct the desired baseband signal. Without the reconstruction filter, the baseband signal contains many undesired components. It is understood in the art that the conversion clock generally has to be of significantly higher frequency than the baseband rate in order to produce enough frequency separation between the baseband and the clock/aliasing components. This thereby allows the implementation of a low pass filter with enough rejection to remove the undesired components without adding significant amplitude and group delay to the desired baseband signal. Interpolating DACs that accept a digital baseband signal at a lower rate and multiply the sample rate (conversion clock) by 2 or 4 times are now common. They typically provide an interpolation according to a sin x/x curve to fill in the additional sample values. This simplifies the reconstruction filter and reduces the processing requirements that would be required to produce a higher sampling rate signal. These methods are based on the use of a DAC and require reconstruction filtering of the output to achieve the desired signal.